ABOUT ME

David Rosocha.

I’m an Electrical Engineering and Computing Technology student at the University of Ottawa, focused on FPGA design, verification, and computer architecture.

I’ve worked on FPGAs at Ciena and satellite systems at Telesat. I now research neuromorphic hardware at Carleton’s SHaRe Lab and silicon photonics at the National Research Council Canada. I also lead uODD, the digital design club I founded at uOttawa.

View the TPU project View resume ↗

Based in Ottawa · Graduating May 2028

**David Rosocha**Electrical engineering & computingView original 3D desk

WHERE I’VE CONTRIBUTED

CienaTelesatNRC Silicon photonicsSHaRe Lab ML HardwareuODD Founder

01 / FEATURED PROJECT

AI on an FPGA

View source ↗

01 — FPGA transformer accelerator

FEATURED PROJECT · 2026

FPGA Transformer
Accelerator (TPU)

A TPU-style accelerator on a Basys 3 FPGA, offloading transformer attention over UART.

8 × 8 systolic array with 64 MAC processing elements.
Double-buffered tiling for matrices up to 64 × 64.
UVM verification against a golden reference model.
Divider-free softmax with <0.9% mean error.

SystemVerilogUVMVivadoPyTorch

64MAC processing elements

<0.9%mean softmax error

Explore the architecture ↗Watch the build 100k+ views in its first week ↗

INSIDE THE DESIGN An 8 by 8 array of 64 multiply-accumulate processing elements

ARTIX-7 / BASYS 3SYSTEMVERILOG

02 / EXPERIENCE

Experience & research

JAN — AUG 2026Co-op · Ottawa

Ciena

FPGA Design & Verification

Built UVVM environments for the FPGA logic behind Hyper Rail, verifying functional correctness, interface compliance, and timing behavior.
Developed constrained-random stimulus and protocol agents to drive coverage closure and catch functional and timing bugs.
Built a SystemVerilog hardware tracer capturing and timestamping up to 256 live signals at sub-10 ns resolution, with signal, vector, AXI, and I²C triggers.
Implemented AXI-Streaming and MPI interfaces for DMA transfer to an external CPU, enabling signal analysis on Linux workstations.

UVVMSystemVerilogAXI-StreamVerification

SEP 2026 — PRESENTResearch

National Research Council Canada ↗

Silicon Photonics Researcher

Designing silicon nitride integrated photonic devices for on-chip sensing.
Using Lumerical for simulation and KLayout for device layout.

Supervised by Dr. Ross Cheriton.

Silicon photonicsLumericalKLayout

SEP 2026 — PRESENTResearch

SHaRe Lab · Carleton University ↗

ML Hardware Researcher

Neuromorphic hardware

Designing an event-driven audio encoder in RTL using spiking neural networks, targeting FPGA implementation for a conference submission.
Implemented a multiplier-free leaky integrate-and-fire neuron in SystemVerilog.
Constrained the discretized decay coefficient to a power of two, reducing the datapath to adders, a shift, and a comparator—with zero DSP slices inferred.

SystemVerilogSpiking neural networksFPGA

MAY — AUG 2025Co-op · Ottawa

Telesat

LEO Satellite Bus & Systems Engineering

Developed a Python coverage simulator for 1,400+ LEO satellites, replacing commercial tooling and improving runtime performance.
Built an optical inter-satellite link framework modeling azimuth, Doppler shift, and alignment to assess crosslink feasibility.
Developed an electrical power simulator modeling dynamic power flow, eclipses, and battery degradation for spacecraft trade studies.

PythonNumPyMATLABSystems engineering

View simulation visuals

Satellite constellation visualization — LEO constellation coverage

Optical inter-satellite link geometry — Optical inter-satellite links

DEC 2024 — PRESENTLeadership

uOttawa Digital Design Club ↗

Founder

Founded uODD, the first digital design club at uOttawa, growing it to 160+ members in eight months.
Teach Verilog and FPGA development through practical workshops.
Coordinate workshops and author open-source curriculum with Ciena and Synopsys.

TeachingDigital designCommunity

03 / EDUCATION